1. Field of the Invention
The present invention generally relates to methods for manufacturing semiconductor devices. More particularly, this invention relates to methods for manufacturing CMOS devices comprising a gate stack, the gate stack comprising a metal gate electrode featuring dual work function and the CMOS devices made thereof.
2. Description of the Related Technology
Up to now, semiconductor industry remains driven by scaling geometric dimensions of metal-oxide-semiconductor field-effect-transistors (MOSFETs). With traditional MOSFET-technology, using silicon dioxide (SiO2) as gate dielectric and polycrystalline silicon (poly-Si) as gate electrode, a lot of problems occur when scaling down to 100 nm or below.
As the gate dielectric thickness is reduced, an exponential increase of gate direct tunnelling currents occurs. One solution to solve this problem is the introduction of so-called high-k dielectrics as gate dielectric. A high-k dielectric is a dielectric featuring a dielectric constant (k) higher than the dielectric constant of SiO2, i.e. k>3.9. High-k dielectrics allow for a larger physical thickness (compared to SiO2) for obtaining a same effective capacitance than can be obtained with a much thinner SiO2 layer. The larger physical thickness of the high-k material will reduce gate leakage currents.
With the introduction of the high-k materials a new problem arose, namely the Fermi level pinning effect, originating in the interaction between high-k material and polysilicon. Fermi level pinning is a fundamental characteristic of the polysilicon/metal oxide interface that causes high threshold voltages in MOSFET devices. A solution to this problem is the introduction of metals as gate electrode.
By introducing metal gates, the threshold voltage of the MOSFET becomes controlled by the metal work function. Regarding metal gate electrodes, tuning of the effective work function is not straightforward as a different effective work function is needed for NMOS than for PMOS. This requires now a (n-type) metal (replacing poly-Si) that works for nMOSFET (i.e. an effective work function preferably between about 3.9 eV and about 4.5 eV) and a (p-type) metal that works for pMOSFET (i.e. an effective work function preferably between about 4.7 eV and about 5.3 eV). Whereas the work function of polysilicon can be tuned by ion implantation, the work function of a metal is a material property which cannot be changed easily.
A possible solution is the use of two metallic materials with different work functions in order to achieve the right threshold voltages for both NMOS and PMOS, also often referred to a dual work function CMOS device. A possible integration scheme is described in an article of Z. Zhang et. al. in “Integration of dual metal gate CMOS with TaSiN (NMOS) and Ru (PMOS) gate electrodes on HfO2 gate dielectric” published in VLSI Tech. Digest, pp. 50-51, 2005. In this integration scheme a first metal layer is deposited on the gate dielectric layer. After partly removing the first metal layer from either NMOS or PMOS side, a second metal layer with a different work function compared to the first metal layer is formed on top of the exposed gate dielectric layer and the remaining first metal layer. Unfortunately, this involves exposing the gate (high-k) dielectric layer to an etchant, leading to dielectric thinning and reliability problems. This integration strategy also requires several patterning, etch and gate stack deposition processes.
The introduction of new gate materials, such as high-k gate dielectrics combined with metal gate electrodes, is not simple, since problems may occur in the traditional gate-first fabrication process steps like etch and strip. Hence, for the integration of high-k gate dielectrics and metal gate electrodes in a complementary metal-oxide-semiconductor (CMOS) device, new manufacturing-friendly alternatives have to be introduced in the process flow. Although already some possibilities are available in the state-of-the-art for the integration of metal gate and high-k dielectric in CMOS devices, there is a need for simplified integration schemes for high-k/metal semiconductor device.